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TTTC's Electronic Broadcasting Service |
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12th IEEE Workshop on Silicon Errors in Logic System Effects |
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CALL FOR PAPERS
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NEW! Special session at DSN for best SELSE papers! The growing complexity and shrinking geometries of modern manufacturing technologies are making high-density, low-voltage devices increasingly susceptible to the influences of electrical noise, process variation, transistor aging, and the effects of natural radiation. The system-level impact of these errors can be far-reaching. Growing concern about intermittent errors, unstable storage cells, and the effects of aging are influencing system design and failures in memories account for a significant fraction of costly product returns. Emerging logic and memory device technologies introduce several reliability challenges that need to be addressed to make these technologies viable. Additionally, reliability is a key issue for large-scale systems, such as those in data centers and cloud
computing infrastructure. |
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Authors are requested to register to
submit a paper by December 14, 2015. The paper submission deadline is January 4, 2016. Papers will be considered for both oral and poster presentation, and all accepted submissions will be distributed to SELSE participants. Authors will be notified by February 23, 2016. Final papers are due on March 8, 2016. |
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Important dates: |
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Organizing Committee |
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| For more information, visit us on the web at: http://www.selse.org |
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The 12th IEEE Workshop on Silicon Errors in Logic System Effects is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC). |
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IEEE
Computer Society- Test Technology Technical Council |
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